The reliability of memory devices is degraded due to the fine process by which they are made and due to their incorporation of multi-level cells (MLCs) for increasing the integration density of the memory devices. The fine process causes the circuit linewidth to be reduced, which leads to the cells being vulnerable to cell-to-cell interference. The use of MLCs causes spacing between levels to be reduced, which increases an overlap area between adjacent levels that can degrade reliability. In the situation where errors of a memory device itself have increased, an error correction code (ECC) technique should be used to ensure a high level of reliability of a data storage device incorporating one or more of the memory devices. In recent years, many studies have been conducted on an LDPC decoder to enhance an ECC function of read performance of a NAND flash memory device. Such LDPC decoders are currently used in flash memory devices for this purpose.